|
Qufei Wang |
Vice Prof. Dr.
|
|
|
 |
|
University of Electronic and Science Technology of China. No. 2006, Xi Yuan Road, High-Tech- Zone(West) |
|
Chengdu |
|
611731 |
|
P.R.China |
 |
Dr. Qufei Wang is a professor of University of Electronic Science and Technology of China. From 2001, the focus of his research is computer architectures, especially the "memory wall" problem. Currently, DRAM latency is the bottleneck of CPU performances. Due to the memory latency, most of the time CPU cores are idle. Faster and more CPU cores just idle more and generate no contribution to user available computing power. This problem is known as the “Memory Wall”. He did a lot of experiments and examined the memory traces of many programs. He found a pattern in the memory accesses of programs which is named the “principle of short lifetime”. This discovery forever rewrote the textbook. Based on this discovery he invented a new CPU cache replacement algorithm, which achieved 50% fewer cache misses for network applications and 30% fewer cache misses for 3D graphics and multimedia applications. This is by far the biggest progress in 30 years. The hit rates of the new CPU cache are very close to those of the offline optimal replacement.
He is planning a general purpose CPU using the new CPU cache. He plan to modify the OpenSparc core and replace some features of the Niagara T2. Due to the new CPU cache, the planned CPU will be twice more powerful than Intel’s. And, he are going to reduce the speed and thus reduce power consumption of the CPU below 10 watts without hurting the performance. The extreme low power of the planned CPU will be a very competitive choice for mobile and wearable computers. It will give mobile and wearable computers computing power comparative or even greater than PCs. He expects that more and more computing will be transferred to mobile computers due to the powerful new CPU.
[1]U.S. Patent: System and Method for Cache Management, Application Number: 20070198779. |
|
|
|
Contact 
